[Pc_Support] It's clear Intel is now the follower ...

[Bryan J. Smith]

Well, after reading up on IDF -- I (among others) clearly see that
Intel is the follower now.  They have to follow on anything AMD does
and try to work around limitations in their approaches, using whatever
they can.

It does look like Intel will beat AMD to quad-core by 6 months, at
least in first product.  They might beat them to volume by 3 months.
How?

By leveraging their 18 month lead in fabrication.  Intel's quad-core
isn't quad-core, it's two separate dual-cores on the same package.
While Intel downplays what that means, it's clearly a major bottleneck
with their architecture.

Intel has also decided to open up its licensing of its FSB so
accelerators can directly connect like any other CPU.  Unfortunately,
this a joke in comparison to HyperTransport, because Intel hasn't
addressed any of the coherency issues in hardware.  It's all in
software.  Otherwise we wouldn't even be using PCIe for video.

It makes good marketing, but substance is rather lacking.  Intel has
really stooped to some all-time lows now, with tactics that you'd
expect out of the #2 innovator.  Just 5 years ago we'd see AMD making
some jokes at Intel's expense.  Now Intel's own managers are the ones
doing the "I hate AMD" and other, childish gimmicks.  Says world's
about how the world has flipped 180.

But Intel has their cash, although AMD isn't strapped like it used to
be.  Which leaves Intel with their fabrication lead, and their
newfound desktop/computational advantage -- at least per-MHz.

But on the scalable and I/O front, there's a lot of issues, and Intel
knows it.  The fact that they are jumping to quad-core without really
designing quad-core means they might have some very serious issues in
doing it using the shared, front-side bottleneck approach.  I heard
the reason for dual-FSBs was their work-around for quad-core as much
as adding a little more I/O.

All at the same time, AMD can go 16-way core with their on-die,
switched interconnect**.

-- Bryan

**NOTE:  In the past, I have previously mentioned that HyperTransport
is used on-die.  This is incorrect.  The "partial mesh" HyperTransport
is only the system interconnect from outside the package to the die.
Inside of the die itself, a crossbar is used.  The limit is 16-way --
or really 10-13 way CPU + 2-way memory + 1-4 way HyperTransport
tunnel.  This, combined with other letacy addressing, logic, etc...
suggests that "switched" EV6 is used on-die.  In any case, it's a heck
of a lot easier for AMD -- especially with its on-CPU/on-die I/O MMU,
than Intel, to scale, handle complex off-CPU logic, etc..., including
HTX NICs (e.g., existing Infiniband), GPUs (e.g., ATI's forthcoming
2007 design), vector processors (e.g., Cray-MIPS, IBM Power-Cell and
others in 2007+), etc... while scaling to 8+ cores on a single die.