[Pc_Support] Memory Technology and Chip Select -- WAS: Rules-of-thumb on upgrading components for an older mainboard ...

[Bryan J. Smith]

William A. Mahaffey III wrote:
> The last 2 paragraphs bring up another point. I have seen some AM2
> boards on NewEgg [1] that claim up to 16 GB of RAM on only 2 slots,

Yeah?  So?

> and almost always 16 GB w/ 4 slots.

Huh?  Who says?  Just because 4GiB DDR DIMMs are the biggest right
now, and even 4GiB DDR2 DIMMs are rare, doesn't mean JEDEC hasn't
spec'd DDR2 to support much larger modules.

Without putting you through a couple of logic + system design EE or
EET (technology) courses, I will attempt to "dissect" elementary
memory controllers -- IC width, chip select and other detail.

SDRAM ICs are organized into combinations of 32-bit banks -- either 2
banks per unbuffered 64-bit wide, or 4 banks of registered/buffered
128-bit wide, channels per 64-bit DIMM.  That's before we talk ECC
(which is 72-bit or 144-bit, respectively).

The ICs themselves are often 4-bit (x4), 8-bit (x8), 16-bit (x16) or
possibly even 32-bit (x32).  To organize them into 64-bit, you need 16
x4 ICs, 8 x8 ICs, 4 x16 ICs or 2 x32 ICs.  Double for
registered/buffered.

Now let's say we have a 8GiB DIMM.  Let's assume it uses a 16 x8 ICs
-- 128-bit / 16 byte wide, registered/buffered -- which would be 4Gib
(as in giga_bit_) SDRAM Technology.  Standard page size in memory is
typically 4KiB (or a multiple of it) on most architectures.  8GiB / 16
/ 4096 = 2^33 / 2^4 / 2^12 = 2^17

I only need 17 pins on the SDRAM ICs themselves for addressing, on a
registered/buffered (128-bit) DIMM.  If the DIMM is
non-registered/unbuffered (64-bit), then 17 pins of addressing at the
individual SDRAM IC gets me a maximum of 4GiB.  The only other pin
that goes active is the actual chip select, which I use with a
decoder.

The ICs themselves are 4Gib SDRAM Technology, because they hold 4
billion cells.  Organized into a 64-bit (8 byte) DIMM, that is 4Gib *
8 / 8bits/byte = 4GiB.  Using a registered/buffered DIMM, which can be
up to 128-bit (16 byte), I can get a 8GiB DIMM.

Looking at the 4Gib SDRAM Technology, which is 512MiB, of 4KiB pages,
I only need 4Gib / 4096 = 512MiB / 4096 = 2^29 / 2^12 = 2^17 -- again
17 pins.

On the DIMM, I have 4GiB of 4KiB pages.  I need 4GiB / 4096 = 2^32 /
2^12 = 2^20 -- 20 pins.  I use the 17 for the first 2^17 (131,172)
pages in each 4GiB IC.  I then use the next 3 for the 3:8 decoder on
the DIMM which runs to the CS (chip select) on each IC.  In the case
of registered/buffered, there is an additional CS line to switch
between the two.

[ NOTE:  SDRAM is actually organized in 32-bit banks, and not the full
64-bit wide DIMM, so it's a bit more complicated than that.  But I
over-simplified here for a reason. ]

> Is this a typo, or are the standards for  DDR2 more expansive size-wise ?

Don't know, haven't read the JEDEC PC2 (DDR2) standards in awhile.

> Also, what about speeds vs RAM mass ?

What do you mean by RAM "speed" and what do you mean by "RAM mass"?

There is a chronic plague that hits enthusiasts called "I invented yet
another memory term today" -- density, double-stack, etc... which are
absolutely _useless_.  You really can't use any terminology without
understanding how memory controllers are designed, how they address
banks of memory, which are simply traces run to individual ICs with a
few chip selects.

So, if you mean "SDRAM Technology" when you say "mass," and you are
using a registered/buffered DIMM, then for a 8GiB module, only 4Gib
SDRAM Technology is needed.  I.e., each IC can be up to 4 billion bits
(4Gib), organized into a 128-bit (16 byte) wide interface.  For
non-registered/unbuffered, I can get a 4GiB module, using ICs of 4
billion bits (4Gib SDRAM Technology) into a 64-bit (8 byte) wide
interface.

BTW, the 128-bit v. 64-bit has on the 64-bit DIMM itself has _nothing_
to do with "dual channel" or anything (that's completely _different_).
 It has to do with the fact that registered/buffered can do extra
interleaving inside the DIMM (although it can use a 64-bit wide
without it too).

"Dual-channel" has to do with the interconnect from the DIMMs to the
Intel MCH (memory controller hub) or AMD processor (which is directly
connected to the memory).