[Pc_Support] Re: nforce4 topology

[Bryan J. Smith]

On Sun, 2006-01-08 at 08:29 -0800, Jimmy V. wrote:
> Hello!  I've been reading your blog since I came across it not to
> long ago and find it very informative!
> However, I'd like to make a slight correction regarding the device
> topology of the Nforce4 chipsets:
> None of the onboard devices are actually PCI-E devices i.e. sata/net/usb/p2p
> bridge/etc
> They are logically (but not physically) pci devices individually  brigded to HT
> via their proprietary internal MCP bus, so there are
> no lanes allocated for them out of the x20 total per root-complex (each Nforce
> chip/MCP .. "CK8-04" or the extra "IO-4" echnically).
> In fact you can verify this yourself with lspci.  Using lspci -tv 
> will show that the onboard devices are all top level devices.  Any
> PCI-E device *must* be under one of the four possible root ports 
> (virtual bridges) in each root complex, which would have a device of 0x5D and
> located at one of bus,dev,func: 0,E/D/C/B,0.. unless 
> it has changed for the nforce 410/430 versions.  Furthermore, pci 
> config registers will also indicate if a device is PCI-E or PCI.
> Just letting you know so you don't think they are bottlenecked by 
> a x1 link :D

Interesting.  So they are directly gluing the logic to the HT?
I'll have to research this more, thanx.

-- 
Bryan J. Smith   mailto:b.j.smith at ieee.org
http://thebs413.blogspot.com
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